TU BCA 1st Semester – Digital Logic Model Question Paper Set 4

Digital Logic Model Question Paper for BCA (Tribhuvan University) – Exam Preparation

If you’re preparing for your BCA Digital Logic exam at Tribhuvan University (TU), Nepal, you’re in the right place! This Digital Logic model question paper is designed to help you revise and practice key concepts, circuits, and Boolean algebra for the upcoming exam. Whether you’re a student aiming to boost your grades or someone looking to understand core topics like combinational circuits, sequential circuits, flip-flops, Karnaugh maps, PLA, PAL, and counter design, this model set has everything you need to succeed.

In this Digital Logic model question set for BCA, you’ll find questions on both short-answer and long-answer formats that focus on:

• Boolean algebra simplifications
• Design and analysis of digital circuits
• Flip-flops (JK, D, T, SR) and their applications
• Karnaugh Maps (K-map) for function minimization
• Counter design (Asynchronous & Synchronous)
• Combinational logic design using AND, OR, NOT, NAND, NOR gates
• Programmable Logic Arrays (PLA) and Programmable Array Logic (PAL) design

This set of questions follows the format of BCA Digital Logic exams at Tribhuvan University, allowing you to familiarize yourself with the types of questions and improve your problem-solving skills. It will also help you understand how to approach complex circuit designs, simplifications, and the application of various logic gates in digital systems.

BCA – Digital Logic Model Question Paper

Time: 3 Hours

Full Marks: 50

Section A: Attempt Any SIX Questions.

(6 x 5 = 30 Marks)

1. Perform binary subtraction using the 2’s complement method:
   101101.110 – 110011.101
   (Show all steps clearly.)
2. What are Universal Logic Gates?
   Explain how the NAND gate and NOR gate can be used to implement any Boolean function.
   (1 + 2 + 2)
3. Simplify the Boolean expression using K-map for the following function F in SOP and POS forms:F=A′B′C+AB′C′+ABC′+A′BCF = A’B’C + AB’C’ + ABC’ + A’BCF=A′B′C+AB′C′+ABC′+A′BC(2 + 3)
4. What is a Decoder?
   Draw the logic diagram and truth table for a 2-to-4 line Decoder with active-low outputs.
   (1 + 4)
5. Define D Flip-Flop.
   Explain the working of the T Flip-Flop with its truth table and logic diagram.
   (1 + 4)
6. Design a MOD-6 counter using JK Flip-Flops.
   Show the state diagram, state table, and timing diagram for the MOD-6 counter.
   (2 + 2 + 1)
7. Design a 4-bit Parallel-In Serial-Out Shift Register.
   Provide the timing diagram for the operation of the register.
   (3 + 2)
8. Explain the operation of a Half Subtractor.
   Provide the truth table and logic diagram for the half subtractor.
   (2 + 3)

Section B: Attempt Any TWO Questions.

(2 x 10 = 20 Marks)

9. Write the difference between PLA (Programmable Logic Array) and PAL (Programmable Array Logic).
   Design a PLA circuit for the following Boolean functions:F1(A,B,C)=Σ(0,2,4,7)F2(A,B,C)=Σ(1,3,5)F_1 (A, B, C) = Σ(0, 2, 4, 7) F_2 (A, B, C) = Σ(1, 3, 5)F1​(A,B,C)=Σ(0,2,4,7)F2​(A,B,C)=Σ(1,3,5)Also, provide the PLA program table.
   (3 + 7)
10. What is the working of a D Flip-Flop?
    Design a Master-Slave JK Flip-Flop using JK Flip-Flops.
    Provide the circuit diagram and the truth table.
    (2 + 8)
11. Write the differences between asynchronous and synchronous counters.
    Design a 4-bit Synchronous Up/Down Counter using T Flip-Flops.
    Provide the circuit diagram, state table, and timing diagram for the counter.
    (3 + 7)

Instructions:

1. All questions are compulsory.
2. Answer each question clearly, showing all steps involved in calculations and simplifications.
3. Use neat diagrams wherever necessary.
4. In Section A, all questions are of 5 marks. You will be required to demonstrate your understanding of fundamental concepts in digital logic, simplifications, and basic circuit designs.
5. In Section B, the questions are more complex and will test your ability to design and analyze digital circuits.

Key Areas to Focus on for Exam Preparation:

• Basic Logic Gates: AND, OR, NOT, NAND, NOR, XOR, XNOR.
• Boolean Algebra: Simplification using Boolean laws, Karnaugh Maps (K-map), SOP/POS forms, and don’t care conditions.
• Combinational Circuits: Adders, Subtractors, Multiplexers, Demultiplexers, Encoders, Decoders.
• Sequential Circuits: Flip-flops (D, JK, T, SR), Counters, Registers, Shift Registers.
• Counter Design: Asynchronous (Ripple) and Synchronous counters, Up/Down counters, MOD counters.
• PLA/PAL: Programmable Logic Devices, design and programming of PLA/PAL arrays.