TU BCA 1st Semester – Digital Logic Model Question Paper Set 1

Digital Logic Model Question Paper for BCA (Tribhuvan University) – Exam Preparation

If you’re preparing for your BCA Digital Logic exam at Tribhuvan University (TU), Nepal, you’re in the right place! This Digital Logic model question paper is designed to help you revise and practice key concepts, circuits, and Boolean algebra for the upcoming exam. Whether you’re a student aiming to boost your grades or someone looking to understand core topics like combinational circuits, sequential circuits, flip-flops, Karnaugh maps, PLA, PAL, and counter design, this model set has everything you need to succeed.

In this Digital Logic model question set for BCA, you’ll find questions on both short-answer and long-answer formats that focus on:

• Boolean algebra simplifications
• Design and analysis of digital circuits
• Flip-flops (JK, D, T, SR) and their applications
• Karnaugh Maps (K-map) for function minimization
• Counter design (Asynchronous & Synchronous)
• Combinational logic design using AND, OR, NOT, NAND, NOR gates
• Programmable Logic Arrays (PLA) and Programmable Array Logic (PAL) design

This set of questions follows the format of BCA Digital Logic exams at Tribhuvan University, allowing you to familiarize yourself with the types of questions and improve your problem-solving skills. It will also help you understand how to approach complex circuit designs, simplifications, and the application of various logic gates in digital systems.

BCA – Digital Logic Model Question Paper

Time: 3 Hours

Full Marks: 50

Section A: Attempt Any SIX Questions.

(6 x 5 = 30 Marks)

1. Subtract the following binary numbers using 10’s and 9’s complement methods:
   101101.110 – 100111.101.
   (Use the complement method and show the steps clearly.)
2. What is a Universal Logic Gate?
   Explain the realization of NAND and NOR gates as universal gates.
   (1 + 2 + 2)
3. Simplify the Boolean expression using K-map for the given function F in both SOP and POS form, including don’t care conditions D:
   F=B′CD′+A′BC′D+B′C′D′+BCD′+ABCD′F = B’CD’ + A’BC’D + B’C’D’ + BCD’ + ABCD’F=B′CD′+A′BC′D+B′C′D′+BCD′+ABCD′
   (2 + 3)
4. Define Encoder.
   Draw the logic diagram and truth table for an Octal to Binary Encoder.
   (1 + 4)
5. What is a D Flip-Flop?
   Explain the clocked RS flip-flop with its logic diagram and truth table.
   (1 + 4)
6. Design a MOD-5 Counter.
   Show the state diagram, state table, and timing diagram for the MOD-5 counter.
   (2 + 1 + 2)
7. Design a 4-bit Serial to Parallel Shift Register.
   Show the timing diagram for the register.
   (3 + 2)
8. Explain the operation of a Half Adder and Full Adder.
   Draw their logic diagrams and truth tables.
   (2 + 3)

Section B: Attempt Any TWO Questions.

(2 x 10 = 20 Marks)

9. Write the differences between PLA (Programmable Logic Array) and PAL (Programmable Array Logic).
   Design a PLA circuit for the following functions:F1(A,B,C)=Σ(2,3,5)F2(A,B,C)=Σ(0,4,5,7)F_1 (A, B, C) = Σ (2, 3, 5) F_2 (A, B, C) = Σ (0, 4, 5, 7)F1​(A,B,C)=Σ(2,3,5)F2​(A,B,C)=Σ(0,4,5,7)Also, design the PLA program table.
   (3 + 7)
10. Define D flip-flop.
    Design a Master-Slave flip-flop using JK flip-flop.
    Provide its circuit diagram and truth table.
    (2 + 8)
11. Write down the difference between asynchronous and synchronous counters.
    Design a 4-bit binary ripple counter with its circuit diagram, state table, and timing diagram.
    (3 + 7)

Instructions:

1. All questions are compulsory.
2. Answer each question clearly and show all steps for calculations and simplifications.
3. Use neat diagrams where required.
4. In Section A, all questions are of 5 marks and are designed to test your basic understanding of digital logic concepts.
5. In Section B, questions are more detailed and require in-depth understanding and practical application of digital circuits.

Key Topics for Exam Preparation:

• Basic Logic Gates: AND, OR, NOT, XOR, NAND, NOR.
• Boolean Algebra: Simplification, Karnaugh Maps (K-map), SOP/POS forms.
• Combinational Circuits: Adders, Subtractors, Multiplexers, Demultiplexers, Encoders, Decoders.
• Sequential Circuits: Flip-flops (D, JK, T, RS), Counters, Registers.
• PLA/PAL: Programmable Logic Devices and their implementation.
• Counters: Synchronous and asynchronous counters, design and timing diagrams.